Usage of FPGA in network security

Abstract

This paper approaches to develop the RSA algorithm using FPGA that can be used as a standard device in the secured communication system. This RSA algorithm is implemented in the FPGA with the help of VHDL and works with radio frequency range to make the information safer. A simple nested loop addition and subtraction have been used in order to implement the RSA operation. This results in less processing time and less space in the FPGA. The information to encryption is in the form of statement or file and the same will appear in the decryption. The hardware design is targeted on Xilinx Spartan 3E device. The RSA algorithm design has made use of approximately 1000 total equivalent gate counts and achieved a clock frequency of 50.00MHz. © 2012 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering.