Design of tunneling field-effect transistors based on staggered heterojunctions for ultralow-power applications

Abstract

This letter presents the design of a tunneling FET with III-V-based tunnel heterojunctions for operation in digital circuits with supply voltages as low as 0.3 V. A representative implementation is predicted to achieve an on-state current drive of 0.4 mA/μm with an off-state current of 50 nA/μm. Comparison with homojunction counterparts reveals that the hetero-tunnel- junction implementations may address better the design tradeoff between on-state drive and off-state leakage. © 2010 IEEE.