A Unified FPGA Realization for Fractional-Order Integrator and Differentiator

5Citations
Citations of this article
6Readers
Mendeley users who have this article in their library.

Abstract

This paper proposes a generic FPGA realization of an IP core for fractional-order integration and differentiation based on the Grünwald–Letnikov approximation. All fractional-order dependent terms are approximated to simpler relations using curve fitting to enable an efficient hardware realization. Compared to previous works, the proposed design introduces enhancements in the fractional-order range covering both integration and differentiation. An error analysis between software and hardware results is presented for sine, triangle and sawtooth signals. The proposed generic design is realized on XC7A100T FPGA achieving frequency of 9.328 MHz and validated experimentally for a sine input signal on the oscilloscope. The proposed unified generic design is suitable for biomedical signal processing applications. In addition, it can be employed as a laboratory tool for fractional calculus education.

Cite

CITATION STYLE

APA

Monir, M. S., Sayed, W. S., Madian, A. H., Radwan, A. G., & Said, L. A. (2022). A Unified FPGA Realization for Fractional-Order Integrator and Differentiator. Electronics (Switzerland), 11(13). https://doi.org/10.3390/electronics11132052

Register to see more suggestions

Mendeley helps you to discover research relevant for your work.

Already have an account?

Save time finding and organizing research with Mendeley

Sign up for free