19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme

Abstract

Resistive RAM (ReRAM) is a promising nonvolatile memory with low write energy, logic-process compatibility, and compact cell area. The 1T1R ReRAM [1-3] fits embedded applications requiring fast read (RD) access time (T AC) and low RD-VDDMIN, particularly for devices powered by batteries or energy harvesters. The cross-point ReRAM [4-6] is meant for high capacities with high RD-VDDMIN and slow TAC. As devices shrink, ReRAMs have higher cell resistance (R) and greater variations in write time and R, which reduces the R-ratio (RH/RL) between the high-R state (HRS, RH) and low-R state (LRS, RL). ReRAM also have a high RL, which enables a larger voltage drop across ReRAM to reduce write voltage and cell-switch (CS) size. Thus, ReRAM macro designs suffer: (1) small sensing margin (SM), limited RD-VDDMIN, and slow TAC due to high-RL and small R-ratio; (2) increase in energy due to large set DC-current (IDC-SET) resulting from wide set-time (TSET) distribution. This study develops a swing-sample-and-couple (SSC) voltage-mode sense amplifier (VSA) to overcome (1), enabling 1.8× greater SM for lower RD-VDDMIN and 1.7× faster TAC across various VDD, compared to conventional differential-input (CD) VSAs. To reduce >99% set energy, we use a 4T self-boost-write-termination (SBWT) scheme to cut off IDC-SET of faster-TSET devices, with an area penalty below 0.5%. A fabricated 28nm 1Mb ReRAM macro achieves TAC = 404ns at VDD = 0.27V and confirms the IDC-SET cut-off by SBWT. © 2014 IEEE.