Source-pull and load-pull characterization of graphene FET

Abstract

This paper presents the characterization of a GFET transistor using a source-pull/load-pull test set. The characterization shows that despite the good fT and fMAX, it is hard to achieve power gain using the GFET device within a circuit configuration. This is due to the very high impedance at the gate making impedance matching at the input extremely difficult. S-parameter characterization is performed and the associated small signal model is developed in order to further analyse and extrapolate the source-pull and load-pull measurement results. A good agreement is observed between small signal model simulation results and source-pull/load-pull measurements. Finally, the model is used to evaluate the optimum power gain of the transistor in a circuit configuration under matched conditions.