Improvements in CPU & FPGA Performance for Small Satellite SDR Applications

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Abstract

The ongoing evolution in constellation/formation of CubeSats, along with a steadily increasing number of satellites deployed in lower earth orbit, demands a generic reconfigurable multimode communication platform. As the number of satellites increase, the existing protocols combined with the trend to build one control station per CubeSat become a bottleneck for existing communication methods to support data volumes from these spacecraft at any given time. This paper explores the software-defined radio (SDR) architecture for the purposes of supporting multiple signals from multiple satellites, deploying mobile and/or distributed ground station nodes to increase the access time of the spacecraft and enabling a future SDR for distributed satellite systems. Performance results of differing software transceiver blocks and the decoding success rates are analyzed for varied symbol rates over different cores to inform on bottlenecks for field programmable gate array acceleration. Furthermore, an embedded system architecture is proposed based on these results favoring the ground station which supports the transition from single satellite communication to multisatellite communications.

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Maheshwarappa, M. R., Bowyer, M. D. J., & Bridges, C. P. (2017). Improvements in CPU & FPGA Performance for Small Satellite SDR Applications. IEEE Transactions on Aerospace and Electronic Systems, 53(1), 310–322. https://doi.org/10.1109/TAES.2017.2650320

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