A 12 bit 150 MS/s 1.5 mW SAR ADC with adaptive radix DAC in 40 nm CMOS

Abstract

This paper presents a 0.9 V 1.5 mW 150 MS/s 12-bit SAR ADC in 40 nm CMOS with adaptive radix DAC, which achieves a synergistic integration of multi-bit-per-cycle and subradix techniques with adaptive error-tolerant redundancies. Alternative-reference-switching (ARS) DAC and adaptive-noise-reduction (ANR) comparator are developed to reduce the DAC effective switching capacitance by 47.4% and comparator power by 37.3%. The achieved peak SNDR, SFDR, and FoM are 61.7 dB, 74.4 dB and 10.3 fJ/conversion-step, respectively.