An efficient un-realization algorithm for privacy preserving decision tree learning using McDiarmid's bound

Abstract

JESD204B transmitter is a part of the serialized data interface between logic devices and data converters bases on the JESD204B standards. The organization, where this project is currently executed, is currently developing the JESD204B Tx and Rx IP for the avionics spacecraft applications where the fail proof and function safe and reliable data communication is essential. The verification of this IP is an important phase in the development wherein it is extremely important to perform rigorous tests on the design to confirm its acclaimed functionality and performance. The verification of an IP of this complexity is done in a systematic and efficient way using the Universal Verification Methodology which is basically constructed using the SystemVerilog. A verification environment is built using the UVM to verify the functionality of the IP. The test cases are written to verify each functionality of the design and the randomized stimuli are applied to cover all the possible input scenarios. The code coverage and the functional coverage is determined and further stimuli are applied to achieve the target coverage. The verification of the JESD204B Transmitter IP is completed with a functional coverage of around 39.17% for each test instance and an overall functional coverage of 100% and code coverage of 94.25%. The verification environment can be reused with minor changes to verify the JESD204B Receiver IP.