Design of low power comparator and binary code encoder for 5 bit parallel adc

Abstract

ADC is one of the important building element many communication systems. Among all the ADC’s flash ADC is preferred for low resolution and high speed applications. Flash ADC consists of comparator and encoder. There are many ways out in the world to implement an encoder and comparator which are the basic parts of ADC. The paper comprises of a comparator and a high speed, low power encoder with a sampling rate of 5Gs/s using different MOS technologies. Full adder based encoder and mux based encoder are designed using CPTL and transmission gate logic. The simulation results shows that power dissipation of the encoder using transmission gate logic is observed to be almost double that of the complementary pass transistor logic. The design and implementation are done by mentor graphics tool using 130nm technology with a supply voltage of 1.2V.