Semidigital PLL design for low-cost low-power clock generation

Abstract

This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology scalability feature. Two design examples in 0.18m CMOS and 65nm CMOS are presented with hardware and simulation results, respectively. © 2011 Ni Xu et al.