Multi-Level Sum of Product (SOP) Network Power Optimization Based on Switching Graph

Abstract

The article presents the methodology of optimization of technology mapping of a multi-output function implemented in the form of sum of product (SOP) networks. The optimization is based on the concept of reducing the switching activity of combinational circuits. The aim of reducing network switching is to limit the consumption of dynamic power. Since dynamic power is one of the components of the total power consumed by digital systems, this leads to an optimization focused on the energy efficiency of digital systems. The basis of the proposed method is the technology mapping using a modified output graph describing the result of minimizing the multi-output function. The modified output graph, in terms of parameters associated with dynamic power, is defined as a switching graph. It was assumed that the key parameter associated with dynamic power is the switching activity of individual nodes of the logic network. The article presents elements of switching graph optimization which lead to the improvement of parameters associated with the dynamic power of the circuit. The essence of the proposed optimization methods is the appropriate movement of products and connections occurring in the logic network. Reducing the number of logic network vertices is also extremely important. The effectiveness of the proposed method was confirmed by the results of experiments performed on selected benchmarks. A significant reduction in the total value of switching activity was obtained for the optimized structures.