Design of watchdog timer for real time applications

Abstract

The Embedded system is employ in safety and critical application, which is greater reliability. The watchdog timers are used in automatic systems to handle the operation time for secure the timer failure. Majority of the watchdog timers used an additional circuit to adjust their timeout position and it will provide limited services in terms of working. This paper presents the architecture of a watchdog timer and also gives the design structure, it will working in safety and critical conditions. The operations are general and it can be used to monitor the working of any processor in real-time application. This paper discussed the implementation of the proposed timer in a FPGA. This will helps to design easily in different applications, it will gives reduces the overall system cost. The watchdog timers is to detect and give response very effectively and also gives the responses of faults by analyzing the simulations.