Analog-digital partitioning for low-power UWB impulse radios under CMOS scaling

Abstract

Ultra-wideband (UWB) impulse radios show strong advantages for the implementation of low-power transceivers. In this paper, we analyze the impact of CMOS technology scaling on power consumption of UWB impulse radios. It is shown that the power consumption of the synchronization constitutes a large portion of the total power in the receiver. A traditional technique to reduce the power consumption at the receiver is to operate the UWB radios with a very low duty cycle on an architecture with extreme parallelism. On the other hand, this requires more silicon area and this is limited by the leakage power consumption, which becomes more and more a problem in future CMOS technologies. The proposed quantitative framework allows systematic use of digital low-power design techniques in future UWB transceivers.