A 16-bit 8-MS/s SAR ADC with a foreground calibration and hybrid- charge-supply power structure

Abstract

In this paper, a 16-bit 8-MS/s successive approximation regis- ter analog-to-digital converter (SAR ADC) with a foreground calibration technique is proposed. A nonbinary searching algorithm is adopted to speed up the conversion rate and overcome the incomplete settling of the reference voltage. A foreground calibration method with low-cost circuitry is implemented to detect the mismatch of the capacitor digital-to-analog converter in calibration mode and compensate for the output code in con- version mode. The simulation results show that the peak signal-to-noise and distortion (SNDR) and spurious free dynamic range (SFDR) are im- proved from 69.98 dB to 91.39 dB and 73.94 dB to 99.41 dB, respectively. Moreover, the proposed ADC uses a hybrid-charge-supply power structure. The sampling circuit operates at 3.3 V to maintain a wide dynamic range, the logic circuit operates at 1.2 V to decrease the conversion time and power consumption, and the total power consumption is 45 mW at 8 MS/s.