Design of a Sampler circuit for Flash ADC using 45nm Technology

Abstract

This paper presents design of a sampler circuit for folding flash ADC. There is a desire for Low power high performance ADC for communication. For low power the size of the ADC should be minimized and for the fast performance flash can be used. Hence to reduce the number of transistors in flash ADC folding network is proposed here. Sampling is the important technique used in the ADC part. In this discussion the sampler circuit includes a differential track and hold switch followed by a variable gain amplifier with a gain of 1 db, a buffer and a folding network. An input voltage of1 V and the sampling frequency of 1GS/s is applied to the sampler circuit. Effective number of bits of more than 5.7 bits is achieved also THD is below -35db in VGA. Buffer achieves a ENOB of 10bits with THD less than -65db. This sampler circuit is designed with the technology of 45nm for coherent sampling. Worst case SNDR is calculated.