0.5-μ1 m 3.3-V BiCMOS Standard Cells with 32-kilobyte Cache and Ten-Port Register File

Abstract

BiCMOS standard cell macros, including a 0.5-W 3-ns register file, a 0.6-W S-ns 32-kilobyte cache, a 0.2-W 3-ns table look-aside buffer (TLB), and a 0.1-W 3-ns adder, are designed with a 0.5-μm BiCMOS technology. A supply voltage of 3.3 V is used to achieve low power consumption. Several Bi-CMOS/CMOS circuits, such as a selfaligned threshold inverter (SATI) sense amplifier and an ECL HIT logic are used to realize highspeed operation at the low supply voltage. The performance of the BiCMOS macros is verified using a fabricated test chip. © 1992 IEEE