A fast-locking low-jitter pulsewidth control loop for high-speed pipelined ADC

Abstract

A fast-locking, high-precision and low-jitter pulsewidth control loop for high-speed pipelined ADC is presented. Only through controlling the delay of rising edge to adjust duty cycle, the clock jitter could be suppressed greatly. An improved charge pump with a follower circuit and self-biased loop was designed to decrease the voltage ripples for higher accuracy and lower jitter. A start-up circuit was adopted to enable the pulsewidth control loop (PWCL) lock rapidly. Using SMIC 0.18 μm 3.3V CMOS Spice process model, the simulation results show that within 180 ns the PWCL can lock the clock duty cycles for the accuracy of 50 ± 1% with 10%~90% input duty cycle from 50MHz to 250 MHz. The rms-jitter is 73 fs at 250 MHz. © IEICE 2012.