A VGA 30fps affine motion model estimation VLSI for real-time video segmentation

Abstract

This paper describes an affine motion estimation processor for real-time video segmentation. The processor estimates the dominant motion of a target region with affine parameters. The processor is based on the Pseudo-M-estimator algorithm. Introduction of an image division method and a binary weight method to the original algorithm reduces data traffic and hardware costs. A pixel sampling method is proposed that reduces the clock frequency by 50%. The pixel pipeline architecture and a frame overlap method double throughput. The processor was prototyped on an FPGA; its function and performance were subsequently verified. It was also implemented as an ASIC. The core size is 5.0 × 5.0 mm2 in 0.18 μm process, standard cell technology. The ASIC can accommodate a VGA 30 fps video with 120 MHz clock frequency. Copyright© 2010.