Level shifter for low power applications with body bias technique

Abstract

In present work three new designs of level shifter in 0.35µm technology using body bias approach have been presented. The level shifters, namely conventional type-I, conventional type-II and contention mitigated have been improved by varying the reverse body bias from 0.1V to 0.5 V. Circuits have been simulated in Spice with TSMC0.35 process technology. Output level of 3.3V has been obtained with input pulse of 1.6V. Modified conventional type-I level shifter shows minimum power consumption of 90.1250pW as compared to 498.33pW for conventional type-I. Further, modified conventional type-II gives minimum power of 480.28pW as compared to 3479pW with existing circuit. Third proposed circuit namely modified contention mitigated level shifter (CMLS) show minimum power consumption of 85.52pW as compared to 493.73pW for circuit without modifications. Simulation results show that proposed circuits are able to shift 1.6V to 3.3V with reduced power consumption with little conciliation in delay.