Design and Implementation of High-Speed Carry Look-Ahead Decimal Adder (CLDA) Using CMOS Technology

Abstract

Decimal arithmetic is gaining more attention by researchers due to their importance in many human-centric applications. Hardware implementations of decimal arithmetic are preferable over their software counterparts as the former leads in performance especially when it comes to real-time applications. Decimal addition is a main decimal operation as most of the other decimal operation can be implemented using decimal addition. Complementary Metal Oxide Semiconductor (CMOS) technology has the advantage of reducing the average power consumption and the propagation delay in digital systems. Decimal adders can be designed as a ripple carry addition (RCA) structure or as a carry look-ahead addition (CLA) structure with the latter being faster with extra hardware cost. This work proposes two CMOS-based carry look-ahead decimal adders (CLDAs) that can be used within any decimal arithmetic unit. Operands of 1-digit size, 2-digit size, 3-digit size, and 4-digit size are investigated. The Boolean logic for each of the proposed CLDAs is developed and the CMOS realization is provided. The circuit of each of the proposed CLDAs is simulated with 45nm technology library using the LT-SPICE spice simulation tool. The simulation shows promising results in terms of speed, power, and power delay product (PDP).