Implementation of efficient architecture of fine grain pipelined lifting scheme based two dimensional discrete wavelet transform

Abstract

Many Discrete Wavelet Transform (DWT) based VLSI architectures have been projected to meet the necessities of the synchronized signal processing. It includes image processing, speech processing, signal and video processing, etc. The practical implementation of DWT has fewer hitches in terms of hardware complexity and memory requirement since it needs to process huge volume of data. The traditional convolution based system needs more multipliers and larger memory and is also not suitable to provide speed or power efficient image or video processing designs. The lifting scheme involves very few mathematical computations compared to the convolution-based DWT. In this paper, we propose an architecture that performs Discrete Wavelet Transform (DWT) using a lifting-based scheme with fine grained pipelined architecture. The basic DWT filters used in image compression are 5/3(lossless) and 9/7(lossy) filters. In fine grain pipelining, multiplier is split into two units by placing the latches on the horizontal cutset across the multiplier. Thus the critical path is reduced to half of the multiplier delay. As a result, it is a speed efficient architecture and is symmetrical with a lower hardware complexity. The architecture is designed using verilog HDL and implemented on Xilinx Spartan 3E FPGA.