Adaptive filter architecture for FPGA implementations

Abstract

Adaptive filters play a Significant role in digital signal processing but their implementation in real time consumes high area and power. Several architectures have been proposed for their real time implementation such as Distributed Arithmetic, CORDIC, Systolic, etc. which reduces the area and improves the speed. All these architectures are mult iplier less and among these, the CORDIC structure is simple and gives reduction in area at the cost of speed. To overcome this drawback, it is modified by implementing it along with Karatsuba algorithm (KA). The combination of KA algorithm and CORDIC structure gives better performance in terms of area and speed. The proposed work is implemented using Xilinx system generator. The structure is tested for different bit representations and the results show that the proposed structure has better performance compared to the existing structures. The proposed structure can be used in applications such as RADAR, Channel Equalizers and Noise Cancellers.