A 7L and 11L High Step-Up SCMLI Topology With Reduced Component Voltage Stress

Abstract

This article proposes a new capacitor-based multilevel inverter topology (CBMLI) with fewer devices and reduced voltage stress on capacitors and switches. In addition, the proposed topology can be configured as either a 7-level (7L) or 11L circuit with a maximum voltage gain of 3 and 2.5 times, respectively. Comparisons are made between the proposed topology and existing recent CBMLI topologies, and various power loss analyses are presented. The capacitance values are determined by selecting the maximum discharging period, and the associated analysis is presented. Using the simulation software MATLAB/Simulink, the performance of the proposed circuit topology is validated, and the same is tested in the hardware setup. The various dynamic performance characteristics, such as loading changes, input variations, and modulation index, are validated, and the resulting data is discussed.