Sub-50nm tri-layered strained Si/SiGe/Si channel nMOSFET

Abstract

Development of a sub-50nm MOSFET on incorporating two strained silicon layers in the channel region has been carried out leading to the advent of 50nm and 100nm channel length devices. Further scalability and device analysis have been due, which has been now the focus of this paper. The effects of strained Silicon-Germanium thickness on the device leakage current have been analyzed and optimized using Synopsis TCAD simulations. The enriched device characteristics for the scaled 30nm device have also been examined in comparison to 40nm and 50nm channel length device MOSFET.