Hardware/software co-simulation in a VHDL-based test bench approach

Abstract

Novel test bench techniques are required to cope with a functional test complexity which is predicted to grow much more strongly than design complexity. Our test bench approach attacks this complexity by using a strong hierarchical architecture, application domain-independent synchronization, reusable modules, and easy incremental extendability based on table-driven techniques. In addition, the integration of VHDL/C co-simulation under the control of the test bench makes it possible to use the hardware model for software testing and vice versa and thus enables extreme reductions in test bench coding. The efficiency of our test bench has already been demonstrated in several industrial projects, among them a four-ASIC ATM board with one embedded core and one external micro controller.