Abstract
There are numerous process integration schemes currently in place for the implementation of 3D-IC. Via first, via middle, via last along with back end of line (BEOL), front end of line (FEOL) and other variations of these approaches. This work will explore the role of wafer bonding, both permanent and temporary, in the fabrication of 3D-IC. Additionally, the materials and process flows used for these processes will be examined in detail. Copyright© (2010) by IMAPS - International Microelectronics & Packaging Society.
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CITATION STYLE
Hermanowski, J., & George, G. (2010). The role of wafer bonding in 3D integration and packaging. In 43rd International Symposium on Microelectronics 2010, IMAPS 2010 (pp. 355–360). https://doi.org/10.4071/isom-2010-wa1-paper1
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