Efficient realization of a novel barrel shifter in cadence SoC encounter

Abstract

Reversible logic has the current development for the reason it consumes low power, which is the minimum requirement in the design of VLSI. A barrel shifter is the one which shift, rotate the data it is designed by using reversible gates. A novel Barrel shifter was designed in which it occupies less area with less delay. The proposed reversible barrel shifter was designed in VERILOG HDL and is simulated in XILINX ISE 12.4 simulator and chip level design was implemented in SoC encounter.