A configuration compression approach for coarse-grain reconfigurable architecture for radar signal processing

Abstract

This paper presents a configuration compression approach for coarse-grain reconfigurable architectures (CGRA) to reduce the context size in configuration caches, and therefore improve the reconfiguration efficiency of CGRAs. Firstly, some kernel sub-algorithms of radar signal processing including FFT, FIR and Matrix Inversion are analyzed, to explore the features that configuration contexts consist of a repetition of same blocks for CGRAs. Then, the approach is proposed to reduce the redundancies in configuration contexts when they are loaded into the configuration cache. The experimental results show that the proposed approach can drastically reduce the redundancies in the configuration context, where the configuration context size can be averagely reduced up to 84.82%.