A novel implant masking processes for double self-aligned 4H-SiC DMOSFETs

Abstract

This paper reports the design and fabrication of a 4H-SiC double implant MOSFET with a novel ion implantation masking process, which eliminates the metal masks in previous approaches. Furthermore, a double self-aligned process is introduced to reduce the cell pitch. The channel length of the device is shrunk by a self-aligned oxidation process and the cell pitch is reduced by an ohmic contact metal self-aligned process. By reducing the cell pitch, the best measured specific on resistance is 85 mω∗cm2 for a 30 μm drift region device. A single zone JTE is used around the device to enhance the breakdown voltage. In this study, the best measured breakdown voltage is 2240 V.