Process optimization of via plug multilevel interconnections in CMOS logic devices

Abstract

This paper reports on the optimization of the device and wiring in a via structure applied to multilevel metallization (MLM) used in CMOS logic devices. A MLM via can be applied to the Tungsten (W) plug process of the logic device by following the most optimized barrier deposition scheme of RF etching 200 A IMP Ti (ion metal plasma titanium) 200 A CVD TiN (titanium nitride deposited by chemical vapor deposition) 2 x 50 A. The resistivities of the glue layer and barrier, i.e., IMP Ti and CVD TiN, were 73 and 280 μΩ•cm, respectively, and the bottom coverages were 57% and 80%, respectively, at a 3.2:1 aspect ratio (A/R). The specific resistance of the tungsten film was approximately 11.5 μΩ•cm, and it was confirmed that the via filling could be performed smoothly. RF etching and IMP Ti should be at least 200 A each, and CVD TiN can be performed satisfactorily with the existing 2 x 50 A process. Tungsten deposition showed no difference in the via resistance with deposition temperature and SiH4 reduction time. When the barrier scheme of RF etching 200 A IMP Ti 200 ACVD TiN 2 x 50 A was applied, the via resistance was less than 20 Ω, even with a side misalignment of 0.05 μm and line-end misalignment of ~0.1 μm.