Bit-Level Systolic Array for Fast Exponentiation in GF(2m)

Abstract

This brief contribution presents a new parallel-in-parallel- out bit-level systolic array with unidirectional data flow for computing exponentiation in GF(2m). The array is highly regular, modular, and thus well suited to very-large-scale-integration implementation. In addition, it can provide the maximum throughput in the sense of producing new results at a rate of one per clock cycle. As compared with a previously known systolic GF(2m) exponentiator with the same throughput performance, the proposed system requires much less chip area, has small latency, and is easier to incorporate fault-tolerant design. © 1994 IEEE