Time-symbolic simulation for accurate timing verification of asynchronous behavior of logic circuits

Abstract

As a novel approach to timing verification of logic circuits, the concepts of time-symbolic simulation are proposed. While a conventional symbolic simulator treats signal values as logical expressions, a time-symbolic simulator treats time as algebraic expressions. The time-symbolic simulator makes it possible to simulate logic circuits precisely and to analyze the condition in which the circuits behave correctly. Algorithms for time-symbolic simulation and its application to hazard detection and verification of asynchronous sequential circuits are described. At present, this approach can only be used to simulate a combinational circuit.