Scaling the Ge Gate Stack: Toward Sub 1 nm EOT

Abstract

In order to introduce Ge in CMOS devices beyond the 14 nm technology node, passivation of the Ge gate stack is required. GeOxSy passivation shows promising Dit distribution especially for NMOS application. Besides the passivation, a highly scaled gate stack is required for the next generation CMOS devices. Scaling of the gate stack can be achieved by several means. The GeOxSy interfacial layer can be thinned down by reducing the temperature of the Atomic Layer Deposition (ALD) of Al2O3. On the other hand, bi-layer stacks were made of Al2O3 and HfO2. The Al2O3 layer thickness was varied between 0 and 10 ALD cycles. We will demonstrate that the thickness of the Al2O3 plays a large role on the interfacial passivation layer quality and hence the mobility. Al 2O3 acts as a barrier against O diffusion in both directions: regrowth of the interfacial GeOxSy during HfO2 deposition and O gettering by the TiW gate during anneal will occur if the Al2O3 layer is too thin. Therefore, the final EOT (Equivalent Oxide Thickness) of the gate stack is a complex interplay between the initial GeOxSy thickness and the Al 2O3 thickness of the bi-layer stack. © 2012 The Electrochemical Society.