Novel 10-nm gate length MoS2 transistor fabricated on Si fin substrate

Abstract

To allow the use of molybdenum disulfide (MoS2) in mainstream Si CMOS manufacturing processes for improved future scaling, a novel MoS2 transistor with a 10-nm physical gate length created using a p-type doped Si fin as the back-gate electrode is presented. The fabrication technology of the ultra-small MoS2 device shows fully process compatibility with conventional Si-FinFET process flow and it is also the first time to realize the large-scale fabrication of the arrayed MoS2 transistors with 10-nm gate lengths. The fabricated ultrathin transistors, consisting of 10-nm gate length and 0.7-nm monolayer CVD MoS2, exhibit good switching characteristics and the average drain current on/off ratio reaches to over 106. This technology provides a promising approach for future CMOS scaling with large scale new 2-D material transistors.