Energy-efficient robust data communication in WSNS (Wireless Sensor Networks)

Abstract

Wireless sensor networks (WSNs) with thousands of sensor nodes are deployed under hostile environments and battery constraints. Sensors have to operate for as long as possible in a WSN because of power constraints. Methods/Statistical analysis: The LEACH (Low-energy adaptive clustering hierarchy) scheme is a clustering algorithm to help increase energy efficiency in WSNs. As the semiconductor technology develops, the feature size of sensor nodes also decrease, which is one of the main factors that deteriorates the reliability of the network. Therefore, a fault detection method is adopted among the sensor nodes in WSNs. Previous studies to reduce the power consumption of WSN nodes and increase the reliability of the network have been inherently conflicted because of the fact that increasing the network reliability leads to more power consumption.Findings: In order to guarantee reliable operation of the sensor nodes, the sensor node or the data transmission between the channels must have error recovery capability to compensate for any failure that may occur in a large network. In addition, these sensor nodes have to operate for as long as possible under power constraints. Error detection and correction methods are applied to WSNs even though they consume more power due to redundant parity bits. This study proposed an error-correcting code (ECC) scheme for use in WSNs and for reducing power consumption. This is rendered possible by simplifying the error detection and correction process in the ECC. In this paper, we analyze the efficiency relationship between a power-efficient clustering algorithm and WSN reliability improvement. We also analyze and model the types of errors that may occur in the links between sensor nodes and nodes in the network. Based on this analysis, we propose an ECC scheme with improved power consumption efficiency. Improvements /Applications: This proposed code is called a cross diagonal parity check code. It has the same parity check overhead as the Hamming code but reduced error-check complexity. The error correcting processing time is reduced from 6-XOR stages to 4-XOR stages (~33%) when compared to the ATM-8 HEC code for 64 bit data.