The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing

Abstract

The development and refinement of net-die-per-wafer yield models during the past 25-odd years are reviewed, and the models are tested for accuracy by comparison with actual yield data from seven separate chip companies. Depending on chip size, the more accurate models are the Poisson and the negative binomial. Several models for line yields in wafer fab are also covered. For predicting yields of larger die area very large scale integrations (VLSI’s), the negative binomial model is the more accurate, but its use may require experimental determination of alpha, sometimes called the cluster parameter, versus chip area for the particular process and factory environment of interest. How an Insystems holographic wafer inspection machine can aid this process is described. Financial payback calculations for cleaner processing machines, and experience curve effects on yields are also discussed. © 1990 IEEE