Optimization of power in 8t sram cell by using transistor stacking effect

Abstract

In recent trends, optimization of power is the major challenge in VLSI Technologies. SRAM is a widely used component in cache memories, CPU registers and also in the design of Random Access Memories. Therefore, it is necessary to decrease the power consumption in SRAM. Because of the scaling of transistors, the leakage current plays a necessary role in the power consumption of the device. In this paper, we focus on enhancing the leakage current by using a Transistor stacking method.