A 10-bit 500-MS/s current steering dac with improved random layout

Abstract

According to the segmented current steering Digital-to-analog converter (DAC), the influence of current mismatch and output impedance of the current array on the linearity of DAC is discussed by theoretical analysis and derivation. An optimized layout plan for the current source array randomizes all these unit current sources corresponding to each thermometer code, which can significantly reduce the fist-order and second-order systematic mismatch errors in the current source array, and improve the linearity performance of DAC. With the segmented structure of 6 bit thermometer code and 4 bit binary code, a 10-bit DAC is realized in a 0.18- mm CMOS by using the above layout plan. The active area of this DAC is 620mm 340mm. Operated at 1V digital supply and 1.8V analog supply, with 500 MS/s sampling rate, the measured power consumption of this DAC is 14.3mW. The measurement results show that the Differential nonlinearity (DNL) and the Integral nonlinearity (INL) of the DAC with this random layout scheme are 0.71 LSB and 1.02 LSB. With 500 MS/s sampling rate and 1.465MHz input frequency, the Spurious free dynamic range (SFDR) and the Effective number of bits (ENOB) are 65.6dB and 9.2 bit, respectively.