Set-triggered-parallel-reset memristor logic for high-density heterogeneous-integration friendly normally off applications

Abstract

Memristor devices are promising as high-density computing logic for non-high-speed normally off applications using heterogeneous technologies. This brief proposes a set-triggered-parallel-reset memristor logic (STPR-ML)-based on back-end-of-line-based bipolar-type memristor devices to reduce the area overhead and increase compatibility with standard and nonstandard CMOS processes. The proposed STPR-ML has two subsets: with and without nonvolatile storage capability. Two types of physical structures are also proposed for STPR-ML: 2-D and 3-D. A test chip using 2-D HfOx memristor devices was fabricated using a CMOS process to confirm the functionality of the nand, nor, and xor gates used in STPR-ML. The proposed STPR-ML achieves a 2 ∼ 8 × reduction in area compared with CMOS logic gates with four or more inputs.