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Using coverage to deploy formal verification in a simulation world

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (2011) 6806 LNCS 44-49
DOI: 10.1007/978-3-642-22110-1_5
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Abstract

Formal verification technology has today advanced to the stage that it can complement or replace simulation effort for selected hardware designs. Yet the completion of a formal verification effort is rarely a requirement for hardware tapeout. Simulation remains the primary verification methodology, and means of deciding when verification is complete. In this paper we discuss how formal verification can be deployed using simulation-based coverage in a simulation-based verification schedule. © 2011 Springer-Verlag.

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APA

Singhal, V., & Aggarwal, P. (2011). Using coverage to deploy formal verification in a simulation world. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 6806 LNCS, pp. 44–49). https://doi.org/10.1007/978-3-642-22110-1_5

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