Advanced Chiplet Placement and Routing Optimization Considering Signal Integrity

Abstract

This article addresses the critical challenges of chiplet placement and routing optimization in the era of advanced packaging and heterogeneous integration. We present a novel approach that formulates the problem as a signal integrity (SI)-aware hierarchical Markov decision process (MDP), leveraging the place-to-route (P2R) algorithm. Our method uniquely incorporates the universal chiplet interconnect express (UCIe) eye mask specifications to ensure compliance with datarate-dependent signal integrity requirements. Tested on ten benchmark problems, P2R achieved superior results with an average eye-diagram aperture of 0.869 unit interval (UI) in a single iteration, outperforming random search and deep reinforcement learning (RL) by 44.8%. By addressing the combinatorial complexity and hard constraints inherent in chiplet-based designs, this approach enables optimization while ensuring compliance with industry standards. This work represents a significant advancement in optimizing heterogeneous integrated systems, addressing challenges that conventional placement and routing methods cannot adequately solve.