FPGA based face detection using local ternary pattern under variant illumination condition

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Abstract

This paper presents the design and implementation of real-time face detection using Local Ternary Pattern (LTP). First, an input image is transferred by the Camlink interface and the image is then downscaled for face detection. A tree-structured cascade of classifiers is used for face detection. We implemented the proposed hardware architecture on a Xilinx Virtex-7 FPGA and the processing speed was adjusted to the frame rate of the camera. The size of the input images is 640 × 480 (VGA) and a larger size can be used without performance loss.

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Byun, J. Y., & Jeon, J. W. (2018). FPGA based face detection using local ternary pattern under variant illumination condition. In Lecture Notes in Electrical Engineering (Vol. 474, pp. 365–370). Springer Verlag. https://doi.org/10.1007/978-981-10-7605-3_60

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