Effects of annealing time on the electrical properties of the Y2O3 gate on silicon

Abstract

Effects of post-deposition annealing time (15, 30, and 45 minutes) have been studied on a Y2O3 film sputtered on a Si substrate. A negative flatband voltage shift was observed in a forward bias direction, indicating the presence of positive charges in all samples. The highest dielectric breakdown field and lowest leakage current density were obtained by a sample annealed for 45 minutes, attributed to the acquisition of the lowest effective oxide charge, interface trap density, total interface trap density, and highest barrier height. It was believed that the formation of Y2Si2O7 and/or SiO2 interfacial layers has contributed to the above-mentioned observation.