Comprehensive Investigation of Security and Quality Metrics for Lightweight Double Arbiter PUF on FPGAs: Design and Analysis †

Abstract

Protecting IoT (Internet of Things) devices against attacks is essential due to the rapid increase in connected devices. This is particularly challenging for lightweight devices with limited hardware capacity, making computationally intensive encryption inefficient. To address this issue, PUF-based security applications can enhance security while reducing resource requirements. The PUF must meet key criteria such as unclonability, unpredictability, and uniqueness throughout its operational lifetime. To achieve this, it is important to minimize unwanted offsets in signal propagation delays caused by unbalanced design strategies and ensure that the PUF responds robustly to physical influences. This paper presents the development and an extensive investigation of a novel 56-bit 2-4 Double Arbiter PUF. Its performance is evaluated on 110 FPGAs with a dataset of 3 million challenge–response pairs (CRPs) under temperature variations in a range from 0 to 50 °C. This study also examines the identification of bit positions with high offsets in order to detect and eliminate potential weaknesses. Furthermore, we extend the 2-4 DAPUF with a lightweight XOR layer to create a 2-4 XOR-DAPUF and improve performance. Our results demonstrate robust and efficient hardware architecture. The optimized 2-4 XOR-DAPUF delivers outstanding performance with 95.85% reliability, 48.09% randomness, and 48.79% uniqueness.