A flexible LDPC decoder architecture supporting TPMP and TDMP decoding algorithms

Abstract

In this paper a programmable and area-efficient decoder architecture supporting two decoding algorithms for Block-LDPC codes is presented. The novel decoder can be configured to decode in either TPMP or TDMP decoding mode according to different Block-LDPC codes, essentially combining the advantages of two decoding algorithms. With a regular and scalable data-path, a Reconfigurable Serial Processing Engine (RSPE) is proposed to achieve area efficiency. To verify our proposed architecture, a flexible LDPC decoder fully compliant to IEEE 802.16e applications is implemented on a 130 nm 1P8M CMOS technology with a total area of 6.3mm2 and maximum operating frequency of 250 MHz. The chip dissipates 592mW when operates at 250MHz frequency and 1.2V supply. Copyright © 2012 The Institute of Electronics, Information and Communication Engineers.