A 40-Gb/s transimpedance amplifier in 0.18-μm CMOS technology

Abstract

A 40-Gb/s transimpedance amplifier (TIA) is realized in 0.18-μm CMOS technology. From the measured S-parameters, a transimpedance gain of 51 dBΩ and a 3-dB bandwidth up to 30.5 GHz were observed. A bandwidth enhancement technique, π-type inductor peaking (PIP), is proposed to achieve a bandwidth enhancement ratio (BWER) of 3.31. In addition, the PIP topology used at the input stage decreases the noise current as the operation frequency increases. Under a 1.8 V supply voltage, the TIA consumes 60.1 mW with a chip area of 1.17 × 0.46 mm2. The proposed CMOS TIA presents a gain-bandwidth product per DC power figure of merit (GBP/Pdc) of 180.1 GHzΩ/mW. © 2008 IEEE.