High-Performance Stacked Dynamic Comparator for Analog to Digital Converters

Abstract

This work briefs the stacked dynamic comparator (SDC) for analog mixed-signal applications. Four-clock switches make it work at high speed with reduced power. The input differential sensing action during pre-charge is performed, and the output voltage is independent of output node capacitance. The parasitic resistance is reduced, due to which the latch delay is also reduced. The stacked latch arrangement makes the leakage power dissipation negligible. The proposed SDC circuit exhibits offset voltage, dynamic power, leakage power, and delay that are 1.34 ×, 0.48 ×, 2.56 ×, and 1.64 ×, respectively, compared to conventional designs. These metrics indicate that the SDC circuit is highly suitable for high-performance sensing applications in ADC. All simulations have been handled by the Cadence virtuoso tool using an industry-standard UMC 65nm technology node.