A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization

Abstract

Bayesian optimization has been successfully introduced to analog circuit synthesis recently. Since the evaluations of performances are computational expensive, batch Bayesian optimization has been proposed to run simulations in parallel. However, circuit simulations may fail during the optimization, due to the improper design variables. In such cases, Bayesian optimization methods may have poor performance. In this paper, we propose a Robust Batch Bayesian Optimization approach (RBBO) for analog circuit synthesis. Local penalization (LP) is used to capture the local repulsion between query points in one batch. The diversity of the query points can thus be guaranteed. The failed points and their neighborhoods can also be excluded by LP. Moreover, we propose an Adaptive Local Penalization (ALP) strategy to adaptively scale the penalized areas to improve the convergence of our proposed RBBO method. The proposed approach is compared with the state-of-the-art algorithms with several practical analog circuits. The experimental results have demonstrated the efficiency and robustness of the proposed method.