Design and performance Analysis of XOR and XNOR Functions at Low VDD Using 130nm Technology

Abstract

In this presented work we designed CMOS exclusive-OR/ exclusive-NOR gates with the increase in performance than the existing method. The main aim of our project is to reduce the power and increase the performance. Two new methods are proposed to implement the exclusive-OR and exclusive-NOR functions on the transistor level. The first method which consists of CMOS Based exclusive-OR/ exclusive-NOR design. In this method we have less power dissipation and delay which leads to less PDP value. The other one is combined exclusive-OR/ exclusive-NOR design which improves the performance of the prior method. It uses the same number of transistors as but with more driving capability additionally. Simulations are verified through 130nm mentor graphics tool.