Design and analysis of wideband low-power LNA for improved RF performance with compact chip area

Abstract

Here, a wideband low-noise amplifier (LNA) based on the two-stage cascade configuration is presented to improve the radiofrequency (RF) performance. With the common gate (CG) input stage, the proposed LNA provides wideband input matching, while the wideband gain response was achieved using the peaking inductors inserted at the drain terminals of each stage. With a standard 0.18 μm CMOS process, the chip area of the proposed wideband LNA is only 0.116 mm2. However, it consumes a 5.4 mW power from a supply voltage of Vdd = 1V. From the post-layout simulation results, it achieves maximum power gain S21 of 11.13 dB at 8.5 GHz, input return loss S11 below -9.44 dB, reverse isolation S12 less than -60 dB, and small group delay variation of ±97 ps across 8.5-20 GHz frequency range. Moreover, noise figure (NF) lies in the range of 2.19-3.23 dB, whereas the NF minimum (NFmin) varies in the range of 1.55-2.91 dB for 8.5-20 GHz frequency range. Apart from this, the proposed LNA achieves an IIP3 of 0.96 dBm, when a two-tone test is performed with a frequency spacing of 50 MHz.